Nonvolatile memory devices can retain stored data even when a power supply is interrupted. FIG. 1 is a layout view of a conventional nonvolatile memory device, and FIGS. 2 and 3 are sectional views taken along lines I-I′ and II-II′ of FIG. 1, respectively. Referring to FIGS. 1 through 3, in a flash memory device which is a typical nonvolatile memory device, a device isolation layer 20 is formed in a semiconductor substrate 10 to define an active region, and a plurality of word lines WL are formed that cross over the active region and the device isolation layer 20. The word lines WL include a plurality of floating gates 32, control gate electrodes 36, and intergate dielectric layers 34, respectively. The floating gates 32 are formed on the active region. The control gate electrode 36 is formed on the floating gate 32 such that it crosses over the active region and the device isolation layer 20. An intergate dielectric layer 34 is interposed between the floating gate 32 and the control gate electrode 36. Tunnel insulating layers 30 are interposed between the floating gates 32 and the active region.
The floating gate 32 may have the same width as a width of the active region thereunder, or a greater width than the width of the active region, such that the floating gate 32 partially overlaps the device isolation layer 20. The device isolation layer 20 may have a protrusion higher than an upper surface of the active region, and the protrusion of the device isolation layer 20 may contact an entire surface or a portion of a sidewall of the floating gate 32.
An interface trap density (Nit) may be used to indicate the reliability of a transistor. In the nonvolatile memory device, the value Nit represents a silicon lattice damage of an interface of a tunnel oxide layer due to FN tunneling. If Nit is high, as the number of write/erase cycle increases, charges become trapped at an interface, gradually decreasing a voltage difference between a write threshold voltage and an erase threshold voltage. As a result, a read margin of program/erase for a memory cell is reduced.
In the nonvolatile memory device, the active region is defined using a shallow trench isolation (STI) process. Here, an edge of the active region may include lattice damage due to a physical stress. When the tunnel insulating layer 30 is formed later, a thickness te of the tunnel insulating layer 30 corresponding to an edge of the active region becomes smaller than a thickness tox of the tunnel insulating layer 30 corresponding to a center of the active region, that is, edge-thinning occurs, as illustrated in FIG. 4. Accordingly, during write/erase operations, an electric field is concentrated and trap density greatly increases in an edge of the active region where the tunnel insulating layer 30 is relatively thin. Since the ratio of an edge to the tunnel insulating layer 30 increases as the active region has a small width, it is estimated that the reliability greatly decreases as a device is highly integrated. Also, as a threshold voltage dispersion of a cell array becomes large, due to a strong electric field formed in an edge of the active region, a decrease of the operating speed of a device may occur.